Burn-in and Test Board Design Guidelines

Generally, line spaces of a minimum 0.010″ can be maintained for differentials of less than 50V. However, Loranger has built boards with up to 1,000-vol differentials with consequent increased trace spacing.

Line widths and spaces of 0.010″ can be easily obtained, however, 0.025″ minimum spaces and traces are preferred to accommodate manufacturing cost and wear concerns. Smaller dimensions add significant cost but Loranger has produced 0.004″ traces and spaces with success.

Where possible, two-sided PC boards with plated-thru holes are preferred for economy, reliability and ease-of-repair; however, multi layers of 4 thru 26 layers are available.

Loranger normally prefers a 0.5″ “circuit-free” zone around the entire perimeter of the PC board, save the edge finger area, for manufacturability, sharpness of the layout and mechanical attachment spacing for the framing, such as the Isolation / Support Frame.

Bulk Decoupling – for low frequency decoupling, use 46 to 200 microfarad capacitors between the supply voltage and common return. These capacitors should be solid tantalum capacitors which have better transient response than most other large value capacitors and put more capacitance into a small package, which simplifies board layout. Half the bulk capacitance should be placed near the point where the supplies enter the board and the other half at the far side of the DUT so the array lies between the bulk decoupling capacitors. It is important that both the capacitance and voltage ratings of solid tantalum capacitors be derated for use at 125°C, the maximum operating temperature specified by most capacitor manufacturers. Although solid tantalum capacitors are expensive, their cost is insignificant when compared to the value of the DUT they protect.

Local Decoupling – to avoid high-frequencies overcomes the voltage spikes which develop on the power supply pins of the memory devices when they are turned on or off by dynamic control signals. Layout the board for a 0.1 microfarad capacitor per DUT. These local decoupling capacitors should be located as close as physically possible to each chip and have the shortest possible traces from their respective power supply to ground. To further reduce inductance, these traces should be as wide as room will permit.

For soundness of solder joints, design with a minimum of 50% more pad area than the PTH area (0.010″ minimum annular ring).

The single most important aspect of successful memory burn-in board design is good power distribution accompanied with carefully designed decoupling and power gridding.

The following are guidelines for the proper techniques to be used when designing burn-in boards for RAMS, ROMs, microprocessors and other electrically-delicate devices. Based upon individual customer requirements, Loranger incorporates these and other (proprietary) techniques to produce high-quality burn-in boards with exceptional signal integrity. Separate cost must be quoted, however, to uniquely tune a design to a specific device type.

Grids for power distribution are important layout considerations. Both voltage and ground buses should be bused up and down the burn-in board throughout every device position. Providing multiple paths through the array reduces the effective inductance of the power distribution system. Traces running the power supply voltages throughout the array should be as wide as possible.

The second most important aspect of successful burn-in board design.

Minimize the use of vias in multi layer designs for circuit integrity and cost.

Minimize the number of feed-thru holes that do not have a component lead soldered into them to enhance reliability.

Solder masks are generally required, however where insulation needs are great or where humidity or other atmospheric contaminates are present, conformal coating may be recommended. Consult Loranger for recommendation of special applications.

In general, the wire sizes selected should be one size bigger than what is required to insure safety, minimize voltage drops and crosstalk between lines. Wire insulation is normally silicone or Teflon plastic for all oven atmospheres up to and including 200°C. Above 200°C, a silicone glass braid is normally chosen for insulation. Finally, standard wire is generally preferred over solid conductors. Outside the oven environment, THHN insulation is normally used

The foregoing rules are general, sound engineering design practices. Unique needs may force the modification or enhancement of these rules. Other concerns for electrical noise, line termination and decoupling may further augment the design and layouts. PTH pads, conductor paths, edge finger plating, nomenclature, solder mask and fabrication details are covered by Loranger’s Manufacturing Process Specifications (MPS #3400 Series).